Semiconductor devices, such as IC and LSIs, are produced in the following process. A photoresist is uniformly coated on an electroconductive metallic layer, an insulating layer and a low-dielectric material layer formed on a substrate, such as a silicon wafer, by CVD vapor deposition process or the like. The photoresist is selectively subjected to exposure and development to form a photoresist pattern. The electroconductive metallic layer, the insulating layer and the low-dielectric material layer formed by CVD vapor deposition are selectively etched by using the photoresist pattern as a mask to form a minute circuit, and the photoresist layer thus becoming unnecessary is then removed with a stripping solution.
It is a trend in recent years that wiring circuits are becoming minute and multilayered as integration degree of semiconductor devices increases and chip size reduces, in which there arise problems in semiconductor devices, i.e., resistance of metallic layers (wiring resistance) and wiring delay caused by wiring capacities. Accordingly, there are proposals of using metals, such as copper (Cu), having resistance smaller than that of aluminum (Al) having been mainly employed as a wiring material, and in recent years, two kinds of devices are being used, i.e., devices using an Al wiring (a metallic wiring using Al as a major component, such as Al and an Al alloy) and devices using a copper wiring (a metallic wiring using Cu as a major component).
Upon forming a Cu metallic wiring, in particular, a process is used in which a Cu multilayer wiring is formed without etching Cu by using a dual damascene process, owing to the low etching resistance of Cu. Various kinds of dual damascene processes have been proposed. One example thereof comprises forming a Cu layer, a low-dielectric layer (e.g., SiOC layer) is accumulated as being multilayered on a substrate, then providing a photoresist layer as the uppermost layer, and thereafter selectively exposing the photoresist layer to light and developing it to form a photoresist pattern (a “first photoresist pattern”). Then, by serving the first photoresist pattern as a mask pattern, the low-dielectric layer is etched, and then the first photoresist pattern is stripped away by O2 plasma ashing treatment or the like thereby to form via holes that connect to the Cu layer on the substrate. Next, another photoresist pattern (a “second photoresist pattern”) is newly formed as the uppermost layer on the remaining multilayer structure, and the remaining low-dielectric layer is partly etched by using the second photoresist pattern as a mask pattern to thereby form wiring trenches that communicate with the above-described via holes. With that, the second photoresist pattern is stripped away by O2 plasma ashing treatment or the like, and then the via holes and the trenches are filled with Cu by electrolytic plating or other method, thereby forming multilayered Cu wiring conductors.
The substrate for use in the process may optionally be provided with a barrier layer (e.g., SiN layer, SiC layer) as an etching stopper layer between the Cu layer and the low dielectric layer. In such a case, via holes and trenches are formed, and then, while the barrier layer exposed out on the substrate is kept as such or after the barrier layer has been removed, the photoresist is stripped away and thereafter the via holes and the trenches are filled with Cu.
In the dual damascene process as above, Si deposition may readily occur, resulting from the low-dielectric layer, during the etching treatment and the plasma ashing treatment for forming the via holes and the trenches, and this may form Si deposits around the opening of the trenches. In addition, a deposition that results from photoresist may also occur. If these deposits are not completely removed, then it causes a problem in that the yield in semiconductor production may lower.
Accordingly, heretofore, O2 plasma ashing treatment has been employed for removal of photoresist patterns and etching residues in conventional patterning for metal wiring. However, with the development of ultra-micropatterning technology, a material having a lower dielectric constant has become used for the low-dielectric layer to be formed on Cu wiring substrates, and at present, a process of using a low-dielectric layer that has a dielectric constant of 3 or less is being developed. It is said that the material of the type having such a low dielectric constant (low-k material) is poorly resistant to ashing or is not resistant to ashing, and when such a low-k material is used, a process not including an O2 plasma ashing step after etching must be employed.
Accordingly, in the art of photolithography for producing advanced micropatterned multilayer semiconductor devices, it is a pressing need to develop a method for stripping a photoresist that exhibits excellent photoresist strippability and etching residue strippability even in a process not including a conventional O2 plasma ashing treatment to the same level as or to a higher level than that in the conventional process of including an O2 plasma ashing step.
In a dual damascene process of using Cu wiring, when a photoresist and an etching residue are stripped away from a substrate having a barrier layer (etching stopper layer) on a Cu layer thereon while the barrier layer is kept remaining on the Cu layer, then the Cu layer may be kept away from direct contact with the photoresist stripping solution during the stripping treatment, and therefore, it is desirable that the stripping treatment is more efficiently attained according to it.
JP-A-11-774180 (Patent Reference 1) discloses a technique of washing a semiconductor substrate having Al or the like metal wiring thereon, with a washing solution containing an oxidizing agent (hydrogen peroxide) before a photoresist is stripped away from it, and then stripping the photoresist from it by the use of a stripping solution. Regarding the stripping solution, Reference 1 discloses, in one line (as example listing) in its [0007], a tetramethylammonium hydroxide (TMAH)-based stripping solution such as that in JP-A-63-147168 (Patent Reference 2), along with an alkanolamine-based stripping solution and a fluorine-containing stripping solution also disclosed therein. However, in Patent Reference 1, only monoethanolamine-based stripping solutions are actually tested and confirmed in point of their effects, and Patent References 1 and 2 do neither describe nor suggest at all a photoresist stripping method suitable to a dual damascene process that is targeted by the present invention.
JP-A-11-233405 (Patent Reference 3) discloses a method for producing semiconductor devices, which comprises dry etching a semiconductor substrate having an Al or the like metal wiring thereon, then washing a photoresist pattern with a washing solution that comprises an oxidizing agent and an organic acid, and thereafter stripping it with a resist stripping solution. Also in this publication, only monoethanolamine-based stripping solutions are actually tested and confirmed in point of their effects, and this publication does neither describe nor suggest at all the photoresist stripping method suitable to a dual damascene process that is targeted by the present invention.    Patent Reference 1: JP-A-11-74180    Patent Reference 2: JP-A-63-147168    Patent Reference 3: JP-A-11-233405